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0 PrefaceVOD (Video on Demand) technology provides people with an interactive way to obtain information, and continues to expand its application scope and influence as technology improves. The traditional VOD system mainly uses the server as the information source of the video, and is broadcasted on the local area network, and is suitable for serving a residential community or a public institution. For environments with lack of network support and mobility, such as public transportation, traditional VOD systems are obviously difficult to implement.
This paper proposes Altera's SOPC (on-chip programmable system) solution for specific user environments, using NiosII soft core processor and FPGA (field programmable gate array) for flexible configuration, rich IP resources, hardware design and software programming. Features, through the expansion of the IDE (integrated development environment) interface, using the hard disk as a storage medium to achieve the design of multi-channel VOD system. The system is small in size and relatively low in cost, reflecting the advantages of embedded electronic products. Compared with the traditional VOD system, the scope of use is more targeted, the assembly is more flexible, the upgrade and expansion are more convenient, and it has a broad prospect.
1 system function division
The system can be divided into four parts: the system control core, the multi-channel video data reading unit, the video decoding module and the user-on-demand terminal.
1.1 System Control Core
The system uses the Nios II soft core as the control core, and is mainly responsible for hard disk initialization, extracting video program cluster chains, generating program lists, and human-computer interaction control. After power-on, the Nios II controller first initializes the transfer mode and read/write status of the hard disk, then reads the master boot record, addresses the operating system boot record area of ​​the basic partition, and calculates the reserved sector and FAT (file allocation table) size. Get the FAT and root directory entries respectively. After analyzing the files on the directory tree, the file name of the video file and the first cluster of the file are extracted, and the FAT is searched again according to the pointer of the first cluster, the cluster chain of the file is traced out, and finally written into the flash memory. After the above work is completed, the interrupt is initialized, the user is polled, the user is requested to wait, the user command packet is analyzed, and a corresponding response is made.
1.2 Multi-channel video data reading
In order to achieve access to massive video data, the system needs to expand the hard disk as a storage medium. The user-defined hard disk DMA (direct memory access) control module realizes reading and writing of hard disk data. The function includes providing an interface for controlling the hard disk and multi-channel data output for the upper layer program, and generating a hard disk DMA operation state machine signal. After the data is read from the hard disk, it is alternately stored in two SRAMs in a ping-pong operation, and the data in the memory is arranged in parallel according to the corresponding output port. At the same time, according to the demand requirement of the user terminal, the data is fanned out to the on-demand port.
1.3 Video decoding
The system uses an externally extended video decoder board as a hard decoding module. The decoder chip is the LSI LOGIC CL680 video CDMPEG 1 audio/video decoder. The chip is based on the CL480/484 architecture for MPEG-1 audio/video decoding, integrated digital NTSC/PAL encoding and enhanced KTV functionality.
1.4 User on-demand terminal
In order to solve the problem of long-distance communication of multi-user terminals, the system uses RS-485 transceiver as a bridge between the host and the user's on-demand terminal. The RS-485 transceiver uses balanced transmit and differential receive, has the ability to reject common-mode interference, and the receiver's high sensitivity enables detection of voltages as low as 200 mV, greatly improving signal propagation reliability.
The communication method between the host and the terminal adopts a communication protocol similar to the token bus. The host continuously sends out the query packet. The client that receives the query packet is given the right to send the control command. The client can choose to send the command or directly discard the query packet. This prevents multiple clients from sending data to the bus at the same time, causing the communication to fail. Case.
The system adopts the MB90092 video character superimposition module to superimpose the function menu on the user terminal screen to establish a friendly user operation interface, and the user can perform on-demand operation through the control panel.
2 system design
2.1 system hardware structure
The system hardware structure is shown in Figure 1.
In order to realize the control of the hard disk and the ping-pong control of the two pieces of memory, the system uses a customized DMA control module, which is linked to the Avalon bus in the form of user logic through the SOPC Builder software.
2.1.1 DMA Control Module
The block diagram of the DMA control module is shown in Figure 2.
The main function of the DMA control module is to control the hard disk to perform concurrent transmission of multiple video data. In order to ensure video quality, it is necessary to consider the increase in data read and write speed. The system adopts the DMA module written in accordance with the ATA/ATAPI-6 protocol, and controls the hard disk to transmit data in Ultra-DMA mode, which can achieve a maximum transmission rate of 66 Mbit/s, and satisfies the concurrent transmission of multiple MPEG-1 video streams. In addition to solving the transmission rate problem, the system involves simultaneously processing the reading and writing of multiple data, so the corresponding function sub-module is introduced to control the reading and writing of two SRAMs in a ping-pong operation manner, and the address of the storage partition of the multi-path data is performed. management.
The main submodules of the module are DMA controller, DMA state machine, switch and SRAM controller.
As the interface between the Avalon bus and the hard disk, the DMA controller mainly receives the control commands of the upper layer program, and then reads and writes the control register of the hard disk. Under the control of the Nios II program, the transfer mode of the hard disk is set to the Ultra-DMA mode for data. transmission.
The DMA state machine module is a finite state machine implemented in Verilog HDL (Hardware Description Language) based on the T13 group's release of the ATA (ATA/ATAPI-6) document. After the transfer mode is changed to the Ultra-DMA mode under the setting of the control terminal, the hard disk issues a DMA request to the controller, and the DMA state machine is started. The host sends a response signal to the hard disk. If it is successful, the DMA STOP status is released, and the IDE_HDMARDY is valid to indicate that the host is ready. Then, the data stream flows out of the hard disk and sends a pair of edge latch signals, and the SRAM controller latches the data into the memory under the control of the signal. Until the DMA request ends, the STOP signal takes effect and the DMA transfer ends. The entire process follows the ATAPI-6 protocol and uses Verilog HDL to describe the timing of the hard disk DMA transfer process.
The Switch and SRAM controller modules are mainly responsible for scheduling data between two SRAMs during DMA transfer, thereby achieving ping-pong access to data. The Switch module is used to complete the switching between two RAMs and the partition storage of data. It works in two states: Flag is used as the flag bit. When Flag is 0, the operation of writing RAM1 is performed; when Flag is 1, the operation of writing RAM2 is performed. In the DMA mode, one DMA reads a sector of the hard disk just enough to write a piece of RAM, and the Switch module suspends data writing and waits for an interrupt. When the data in the other RAM is completely read out, the interrupt occurs. At this time, the Switch module exchanges the read/write port addresses of the two pieces of memory.
2.1.2 RAM partition read and write
Since the system needs to provide multi-channel video playback, it is necessary to realize partition reading and writing of each video data in the process of performing DMA transmission. When writing to memory, a dual clock control mechanism is employed. To implement a 32-channel VOD system, divide a 512 kΩ RAM into 32 cells, each with a length of 16 kΩ. The address of the defined RAM is: wraddress2=wraddressl+wraddress
Wraddressl is the base address of each memory partition, and its values ​​are 0 k, 16 k, 32 k, 48 k, ..., 496 k, and an offset address wraddress. The memory partitioning mode is shown in Figure 3.
Define clock C0 as the write memory partition clock, C1 is the write memory offset clock, and C0 frequency is 32 times of write C1. When the offset address is a certain value, the value of the weight address will be traversed once from 0 k to 496 k, that is, each memory cell read and write cycle is written to one unit of each partition.
Similarly, the data in the memory is also read out and sent to the corresponding port. The module uses a counting method of memory address: set the length of the address line to 10 bits, and then swap the address of the lower 5 bits with the address of the upper 5 bits. The purpose is to start counting from the upper 5 bits, and the count is full. To the lower 5 places. The upper 5 bits represent the partition address, the lower 5 bits are the offset address of the partition, and the address is accumulated from the 6th bit. It just traverses 32 partitions, and after completing the high 5 bits, the carryover is carried out to the lower 5 bits of the partition offset address. , indicating that the second memory unit of the next round of partitioning begins to be read. And so on. According to the calculated address, the data of each partition can be sequentially read. The address algorithm diagram is shown in Figure 4.
2.1.3 Shift output module
The main function of this module is to shift the multi-channel data read from the memory under the control of the shunt clock. This module defines a set of shift registers that are 16 bits long. The time and speed of data I/O reading and writing is determined by video_clock. The frequency of video_clock is 12.5 MHz, which is responsible for controlling the synchronization of SRAM_R controller, shift output module and video decoder board. An accumulator counter div3 is also set in the module, and the working frequency is the same as video_clock. When the SRAM_R controller sequentially reads each video file into a register, each clock falling edge is shifted out by one bit until all are removed. If the clock frequency and the buffer memory space are increased, the number of shift registers can be increased, thereby increasing the number of video output ports and increasing the number of system on-demand channels.
2.2 System Software Workflow
The system program is divided into two parts: the host program and the on-demand terminal. The host program mainly implements three functions: managing the hard disk, extracting the cluster chain, playing the program, and on-demand control; responding to the request, the serial port is interrupted. The way to manage the hard disk is mainly through the custom DMA control module to operate the control register of the hard disk, drive the hard disk and access the corresponding sector under the FAT32 file system, trace the cluster chain, extract the cluster chain and write it to the Flash ROM. , ready for playback. The on-demand program is mainly responsible for generating instruction packages. The workflow of the system software is shown in Figure 5.
The system has to process multiple video data, and the video signal has a large amount of data. During the on-demand process, the system must concentrate most of the processor time to process each video signal, and the file name and cluster chain structure of the video file must pass the relatively low speed PIO. Operation to get. In order to solve the bottleneck of cluster chain reading speed, this paper designs a data structure suitable for the application of this system to optimize the management of data and speed up the reading speed. The defined data structures are:
The client's state and playback progress are also recorded and managed by specialized structures. The defined data structures are:
3 Conclusion
SOPC=NiosII Soft Core+FPGA This innovative concept brings great convenience and flexibility to embedded design. With the powerful SOPC development platform and rich IP resources, the system design cycle can be greatly shortened, and the system improvement is also very convenient. This paper proposes to integrate the user-defined hard disk read/write module on the SOPC platform and seamlessly integrate with NiosII, and successfully realize the concurrent on-demand of multi-channel video data.
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