National Semiconductor launches wireless base station IF sampling receiver subsystem
National Semiconductor Corporation (NaTIonal Semiconductor CorporaTIon) announced the introduction of a multi-carrier, multi-standard wireless base station IF sampling receiver reference design kit. This subsystem reference design kit for GSM / EDGE, WCDMA, LTE and WiMAX includes all necessary accessories and tools, including reference design boards, software, circuit diagrams, bill of materials and Gerber files. Engineers who design wireless communication systems can shorten the design time and development cycle of high-performance wireless system receivers by using this subsystem design kit.
This reference design board, model SP16160CH1RB, allows engineers to enter different parameters to quickly test the performance of the IF receive signal path. In addition, as long as this design is equipped with a low-noise, excellent linear RF front-end circuit and a strong filtering IF filter, the sensitivity of the extremely sensitive receiver can be higher than that of the normal and blocked cases. The strict regulations of the multi-carrier GSM standard. The higher the receiver's sensitivity, the higher the base station's transmission capacity and the greater its coverage. These can enable network service providers to provide better services to more users.
The IF line receiver using the SP16160CH1RB reference design has a sensitivity of -105dBm. If the input IF signal is 192MHz, the carrier / noise ratio of the 200kHz channel is 9dB. If the gain of the digitally controlled variable gain amplifier is set to the highest value of 22dB, most of the receiver noise will come from the variable gain amplifier, which is the biggest factor affecting the receiver's sensitivity. If the blocking signal is strong, the gain of the variable gain amplifier can be set to 12dB, while the level of the blocking signal input to the analog / digital converter is maintained at 1.6dBm, which ensures the sensitivity of the SP16160CH1RB reference design circuit board -86dBm. In this blocking situation, the receiver's sensitivity depends on the analog-to-digital converter's spurious-free dynamic range (SFDR).
The SP16160CH1RB reference design requires only a 5V power supply, and other components on the circuit board include a 16-bit, 160MSPS dual-channel pipelined ADC16DV160 analog / digital converter, dual-channel LMH6517 digitally controlled variable gain amplifier, and LMK04031B Clock jitter filter. Due to the extremely high dynamic performance of the analog / digital converter, the digitally controlled variable gain amplifier generates very little noise, and its linear performance is also very ideal. In addition to the extremely low rms jitter of the clock jitter filter, this makes this The reference design as a whole can play extremely excellent performance. If a 192MHz IF signal is input, the signal-to-noise ratio of the ADC16DV160 analog / digital converter is 76.3dBFS, and the spurious-free signal dynamic range is as high as 91.2dBFS; while the LMH6517 has only 6dB of noise and 45dBm third-level output intercept point (OIP3 ), And the rms clock jitter of the LMK04031B clock jitter filter is close to 150fsec.
National Semiconductor also provides the WaveVision 5.1 data capture circuit board and WaveVision 5 software that can capture data and analyze it to simplify the evaluation process of the SP16160CH1RB reference design circuit board. In addition, as long as this design is adopted, the two chips of ADC16DV160 and LMH6517 can be set by using the universal serial peripheral interface (SPI) bus. The SP16160CH1RB circuit board is also equipped with a PIC loader circuit board to configure the LMK040310B chip
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