A Bode plot containing three poles and one zero will be used to analyze the gain and phase margin. Assuming a DC gain of 80 dB, the first pole occurs at 100 Hz. At this frequency, the slope of the gain curve becomes -20 dB/decade. The zero point at 1 kHz causes the slope to become 0 dB/decade, and the gain curve becomes -20 dB/decade over 10 kHz. The third and last pole at 100 kHz eventually changes the gain slope to -40 dB/decade.
It can also be seen that the unity gain point (0dB) intersection frequency is 1MHz. The 0 dB frequency is often referred to as the loop bandwidth. The phase shift diagram shows the effect of different distributions of zero and pole on the feedback signal. The sum of the phase shifts is calculated from the zero poles of the distribution. The pole phase shift at any frequency (f) can be calculated by:
Pole phase shift = -arctan(f/fp)
The zero phase shift at any frequency (f) can be calculated by:
Zero phase shift = -arctan(f/fz)
Is this loop stable? To answer this question, we only need to know the phase shift at 0dB (which is 1MHz). No complicated calculations are needed at all.
The first two poles and the first zero distribution change the phase from -180° to +90°, eventually causing the network phase to shift to -90°. The last pole has a 0dB point in the ten octave. Using the zero phase shift formula, the pole produces a phase shift of -84° (at 1 MHz). Adding the original -90° phase shift, the total phase shift is -174° (that is, the phase margin is 6°). This loop may cause oscillations.
NPN regulator compensation
The connection of the conduction tube of the NPN regulator is a way of sharing the electrodes. An important feature of all common collector circuits is the low output impedance. This means that the poles in the power supply range appear in the high frequency portion of the loop gain curve. Since the NPN regulator has no inherent low frequency pole, it uses a technique called dominant pole compensa TIon. At this point, a capacitor is integrated inside the IC that adds a pole to the low side of the loop gain.
The main pole (P1) of the NPN regulator is typically set at 100 Hz. The pole at 100 Hz reduces the gain to -20 dB/decade to the second pole (P2) at 3 MHz. At P2, the slope of the gain curve is again increased by -20dB/decade. The frequency of point P2 depends mainly on the NPN power tube and the associated drive circuit, so this point is sometimes referred to as the power pole. Since the P2 point appears at a loop gain of -10 dB, it means that the phase shift at the 0 dB frequency (1 MHz) will be small.
To determine stability, only the phase margin at 0 dB is calculated: the first pole (P1) produces a phase shift of -90°, but the second pole (P2) only adds a phase offset of -18°. Move (at 1MHz). This means that the phase offset at the 0dB point is -108° and the phase margin is 72° (very stable). It should be noted that the loop is clearly stable. Since two poles are required, it is possible to make the loop reach a phase shift of -180° (unstable point), and P2 is distributed at a high frequency position, and its phase shift at 0 dB is small.
LDO regulator compensation
The connection of the PNP conduction tube in the LDO regulator is a common emitter. It has a higher output impedance than the common collector method. Low-frequency poles occur at low frequencies due to load impedance and output capacitive reactance. The frequency of this pole (called the load pole, denoted by Pl) is obtained by:
F(Pl) =1/(2Ï€&TImes; Rload&TImes; Cout). From this formula, it can be seen that compensation cannot be achieved by simply adding the main pole.
To explain why this is the case, first assume that a 5V/50mA LDO regulator has the following conditions:
At the maximum load current, the frequency at which the load pole (Pl) appears is:
Pl=1/(2π&TImes;Rload×Cout)=1/(2π×100×10-5)=160Hz
Assume that the internal compensation adds a pole at 1kHz. Due to the presence of the PNP power transistor and the driver circuit, a power pole (Ppwr) will appear at 500 kHz.
Assume that the DC gain is 80 dB. Rl = 100 Ω (value at maximum load current), Cout = 10 uF.
It can be seen that the loop is unstable: the poles PL and P1 each produce a phase shift of -90°. At 0 dB (40 kHz in this case), the phase shift is -180°. To reduce the negative phase shift (to prevent oscillation), a zero must be added to the loop. A zero can produce a phase shift of +90°, which cancels out some of the effects of the two low-frequency poles. Basically all LDO regulators need to add this zero to the loop. This zero is typically obtained by a characteristic of the output capacitor: equivalent series resistance (ESR).
Use ESR to compensate LDO
Equivalent series resistance (ESR) is a characteristic common to every capacitor. Capacitance can be expressed as a series connection of a resistor and a capacitor. The ESR of the output capacitor produces a zero in the loop gain that can be used to reduce the negative phase shift. The frequency value at which the zero occurs is directly related to the ESR and output capacitance values: Fzero = 1/(2π × Cout × ESR). Using the example in the previous section, we assume that the output capacitor value is Cout=10uF and the output capacitor has ESR=1Ω. Then the zero occurs at 16 kHz.
Adding this zero point makes the unstable system a stable system: the bandwidth of the loop increases, so the 0dB intersection frequency shifts from 30kHz to 100kHz. This zero point adds a total of +81° phase shift to 100 kHz. That is, the negative phase shift caused by PL and P1 is reduced. Since the pole Ppwr is at 500 kHz, it only increases the phase shift by -11° at 100 kHz. Accumulate all zeros and poles, and the total phase shift at 0dB is now -110°. That is, there is a phase margin of +70° and the system is very stable. This also explains that an output capacitor with the correct ESR value can produce a zero point to stabilize the LDO system.
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