1 Overview
Vivado HLS is a tool provided by Xilinx and is part of the Vivado Design Suite that can convert C-based designs (C, C++, or SystemC) into RTL design files for implementation on Xilinx All Programmable Chips (VHDL/Verilog or SystemC) ).
1.1 Design Flow of vivado hls
Figure 1 Workflow of vivado hls
The Vivado HLS process is available in three different RTL formats. as follows:
IP-XACT — IP-XACT is a public document specification for the design of IP proposed by the SPIRIT consortium. This is a widely used XML template that describes IP. It is not related to a specific tool and is machine readable.
IP Core - When this option is selected, your IP will be output in a format that can be input to XPS.
SysGen - This option allows you to export the resulting RTL file into a package that can be used in System Generator's design.
1.2 Introduction to TCL Scripts
TCL (originally known as "Tool Command Language" "Tool Command Language", but this is not currently meaning, but we still call it TCL) is a scripting language. Created by John Ousterhout. TCL is very easy to learn and very powerful. TCL is often used for rapid prototyping, scripting, GUI and testing. TCL read "Tickle".
2 Labs2 uses tcl script for c,c++ to RTL level simulation synthesis
Use the project file fir.c fir.h fir_test.c of the previous labs1 to run the tcl script to complete the simulation, synthesis, and implementation of the ip and other actions. It is more convenient and faster to complete our design.
Run_hls.tcl script source code is as follows:
Labs2 project directory as shown below. Include files such as fir.c, fir.h, fir_test.c, out.gold.dat, and run_hls.tcl.
The first step to open vivado hls command prompt as shown below
The second step cd to the labs2 directory
Step 3 Enter vivado_hls -f run_hls.tcl Enter
The entire script runs as follows:
Labs2 directory after the completion of the operation as shown below
Like labs1, we generated verilog files for the csim, sim, syn, impl, and fir filters we needed. Completed the conversion of c into verilog. The next section will demonstrate how to add the fir filter ip and vivado to generate the modelsim simulation library and the joint modelsim simulation fir filter.
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