Hitachi Ltd. announced that it has developed two technologies related to mid-high voltage (about 35 to 300V) transistors. One is a technology in which a plurality of transistors having different source and drain withstand voltages are integrated on one chip, and the other is a technology that can increase the gate-source withstand voltage to 300V.
Both technologies have already been scheduled for adoption and are scheduled to begin shipping within 2011. In addition, Hitachi also announced the two technologies at the 23rd International Symposium on Power Semiconductor Devices and IC's (ISPSD 2011) held in San Diego, California, on May 23rd.
“Technical paper entitled “High Performance Pch-LDMOS Transistors in Wide Range Voltage from 35V to 200V SOI LDMOS Platform Technology†(Paper ID 1009) is a technical paper entitled “Integrating multiple transistors with different source and drain withstand voltages on a single chip.†), The technical paper entitled “Increasing the gate-to-source withstand voltage to 300V†is entitled “300 V Field-MOS FETs for HV-Switching IC†(Paper ID 1027). Both papers are published in “Smart Power Technology 2 Sessionâ€. on.
Changing the drift length of LDMOS The development background of "a technology that integrates multiple transistors with different source and drain withstand voltages on one chip", Hitachi's Nakano Satoshi (Design and Communications Division of Micro Devices Business Unit, Information Communication Systems Corporation) LSI Design Department assumes the position of the Minister, said, "After the simulation of digital and weak currents, the demand for high voltage-to-resistance transistors is also expected to increase. This technology satisfies this requirement."
Ueno said it plans to use this technology for ICs for ultrasound diagnostic devices. It is also desirable for ICs and the like for automobiles. In terms of component prices, "discrete transistor prices are very cheap and the integrated ICs are basically the same. However, since the board area can be reduced to 1/10 or less, the total cost and product size can be significantly reduced" (Ueno).
Different withstand voltages are achieved by changing the layout of the transistor length (ie drift length). Using the same semiconductor process, chips with different voltage-tolerant transistors can be fabricated. Both the p-channel LDMOS and the n-channel LDMOS have confirmed that the transistor can operate with a withstand voltage of 35 to 200V. Since only the drift length needs to be changed, "the development side has the advantage of being able to easily design and verify on EDA tools" (Mr. Kojima Oshima, chief technician of the mixed-signal LSI design department of the Micro Devices Business Unit of the ICT Design Division).
Using LOCOS for Gate Oxide Films "About the technology to increase the gate-to-source withstand voltage to 300V," Ueno said, including the company, many semiconductor manufacturers have already supplied the market with a gate source with a maximum withstand voltage of 200V product. When a higher voltage such as 300V is required, a step-down circuit is generally used to reduce the voltage to 200V of the transistor. However, there is a problem that the power consumption of the buck circuit is high.
This time, Hitachi's board card tester manufacturers wanted to ensure that the requirements for the gate-source withstand voltage of 200V or more were developed. As for other uses, Ueno said it is expected to be used in the field of medical devices. "In the field of medical devices, there is a large demand for transistors with a gate voltage of 200V. If 300V products can be provided, the market can be further expanded" (Ueno). Using the technology developed this time, power consumption can be reduced and IC switches with lower leakage currents can be manufactured.
There are several technologies that increase the withstand voltage from 200V to 300V. Including (1) LOCOS (Local Oxidation Of Silicon) used for isolation so far for a gate oxide film; (2) using an electric field simulator to optimize the length of an extended drain layer, etc.; (3) to make wiring Pattern optimization and so on. “Electric field simulators have been used in commercial products before. This time, by improving the modeling and utilization process, it is possible to reproduce phenomena close to reality†(Oshima). In addition, it is difficult to stabilize LOCOS, and other companies have not yet achieved 300V withstand voltage.
Hitachi measured the transistor characteristics using this technology by applying a voltage across the gate and source. After confirming that the optimized design of the transistor can be in the range of 0V to 300V, the voltage between the gate and the source can be used as the normal operation of the transistor.
In addition, the two technologies announced this time can not be combined. In other words, it is not yet possible to integrate multiple transistors with different source and drain withstand voltages on one chip, and to achieve a gate-source withstand voltage of 300V. "Technically speaking is not too difficult. If there is demand, it will be further developed."
Both technologies have already been scheduled for adoption and are scheduled to begin shipping within 2011. In addition, Hitachi also announced the two technologies at the 23rd International Symposium on Power Semiconductor Devices and IC's (ISPSD 2011) held in San Diego, California, on May 23rd.
“Technical paper entitled “High Performance Pch-LDMOS Transistors in Wide Range Voltage from 35V to 200V SOI LDMOS Platform Technology†(Paper ID 1009) is a technical paper entitled “Integrating multiple transistors with different source and drain withstand voltages on a single chip.†), The technical paper entitled “Increasing the gate-to-source withstand voltage to 300V†is entitled “300 V Field-MOS FETs for HV-Switching IC†(Paper ID 1027). Both papers are published in “Smart Power Technology 2 Sessionâ€. on.
Changing the drift length of LDMOS The development background of "a technology that integrates multiple transistors with different source and drain withstand voltages on one chip", Hitachi's Nakano Satoshi (Design and Communications Division of Micro Devices Business Unit, Information Communication Systems Corporation) LSI Design Department assumes the position of the Minister, said, "After the simulation of digital and weak currents, the demand for high voltage-to-resistance transistors is also expected to increase. This technology satisfies this requirement."
Ueno said it plans to use this technology for ICs for ultrasound diagnostic devices. It is also desirable for ICs and the like for automobiles. In terms of component prices, "discrete transistor prices are very cheap and the integrated ICs are basically the same. However, since the board area can be reduced to 1/10 or less, the total cost and product size can be significantly reduced" (Ueno).
Different withstand voltages are achieved by changing the layout of the transistor length (ie drift length). Using the same semiconductor process, chips with different voltage-tolerant transistors can be fabricated. Both the p-channel LDMOS and the n-channel LDMOS have confirmed that the transistor can operate with a withstand voltage of 35 to 200V. Since only the drift length needs to be changed, "the development side has the advantage of being able to easily design and verify on EDA tools" (Mr. Kojima Oshima, chief technician of the mixed-signal LSI design department of the Micro Devices Business Unit of the ICT Design Division).
Using LOCOS for Gate Oxide Films "About the technology to increase the gate-to-source withstand voltage to 300V," Ueno said, including the company, many semiconductor manufacturers have already supplied the market with a gate source with a maximum withstand voltage of 200V product. When a higher voltage such as 300V is required, a step-down circuit is generally used to reduce the voltage to 200V of the transistor. However, there is a problem that the power consumption of the buck circuit is high.
This time, Hitachi's board card tester manufacturers wanted to ensure that the requirements for the gate-source withstand voltage of 200V or more were developed. As for other uses, Ueno said it is expected to be used in the field of medical devices. "In the field of medical devices, there is a large demand for transistors with a gate voltage of 200V. If 300V products can be provided, the market can be further expanded" (Ueno). Using the technology developed this time, power consumption can be reduced and IC switches with lower leakage currents can be manufactured.
There are several technologies that increase the withstand voltage from 200V to 300V. Including (1) LOCOS (Local Oxidation Of Silicon) used for isolation so far for a gate oxide film; (2) using an electric field simulator to optimize the length of an extended drain layer, etc.; (3) to make wiring Pattern optimization and so on. “Electric field simulators have been used in commercial products before. This time, by improving the modeling and utilization process, it is possible to reproduce phenomena close to reality†(Oshima). In addition, it is difficult to stabilize LOCOS, and other companies have not yet achieved 300V withstand voltage.
Hitachi measured the transistor characteristics using this technology by applying a voltage across the gate and source. After confirming that the optimized design of the transistor can be in the range of 0V to 300V, the voltage between the gate and the source can be used as the normal operation of the transistor.
In addition, the two technologies announced this time can not be combined. In other words, it is not yet possible to integrate multiple transistors with different source and drain withstand voltages on one chip, and to achieve a gate-source withstand voltage of 300V. "Technically speaking is not too difficult. If there is demand, it will be further developed."
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