The second part of the ZedBoard & Zynq series is designed to learn how to program Zynq PL without using ARM PS, and how to use the Xilinx? PlanAhead tool.
Hardware platform: Digilent? ZedBoard
Development environment: Windows XP 32 bit
Software: ?XPS 14.2 +PlanAhead 14.2?
New construction LAB2
In the project settings, you need to select the chip as Zynq.
Select the file type as verilog and the name will be ledwater
After that, the pin information will be prompted. The default is empty, which can then be implemented by verilog code.
After entering ISE, add the source file, the content is as follows
/*
"Step by Step to Learn ZedBoard & Zynq", Part 2: Using Zynq's PL as a Water Light
September 11, 2012 10:31:13
Super group
*/
Module ledwater(
Input BTNU,
Input GCLK,
Output [7:0] LD
);
Wire clk,rst;
Reg [7:0] LD_reg;
Reg [31:0] cnt;
Assign clk = GCLK;
Assign rst = ~BTNU;
Assign LD = LD_reg;
Always@(posedge clk or negedge rst)
Begin
If(rst==1'b0)begin
LD_reg <= 8'b1000_0000;
Cnt <= 32'b0;
End
Else begin
If (cnt == 32'd25000000) begin
Cnt <= 32'b0;
LD_reg <=(LD_reg>>1)|(LD_reg<<7);
End
Else begin
Cnt <= cnt + 32'b1;
End
End
End
Endmodule
Here BTNU is set to reset, GCLK is the clock
Looking at the schematic of ZedBoard, you know that BTNU is low by default.
In order to achieve the rst falling edge reset, the 38th sentence uses a reversal
1 assign rst = ~BTNU;
The shift of the small lamp adopts the mode of “shifting left 1 bit + shifting right N-1â€, the 29th line can be seen
1 LD_reg <=(LD_reg>>1)|(LD_reg<<7);
Set the pin constraints, ucf content is as follows. LOC indicates pin lock and IOSTANDARD indicates pin level. The complete ucf file can be downloaded from the official website of Diligent
NET LD[0] LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0"
NET LD[1] LOC = T21 | IOSTANDARD=LVCMOS33; # "LD1"
NET LD[2] LOC = U22 | IOSTANDARD=LVCMOS33; # "LD2"
NET LD[3] LOC = U21 | IOSTANDARD=LVCMOS33; # "LD3"
NET LD[4] LOC = V22 | IOSTANDARD=LVCMOS33; # "LD4"
NET LD[5] LOC = W22 | IOSTANDARD=LVCMOS33; # "LD5"
NET LD[6] LOC = U19 | IOSTANDARD=LVCMOS33; # "LD6"
NET LD[7] LOC = U14 | IOSTANDARD=LVCMOS33; # "LD7"
NET GCLK LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK"
NET BTNU LOC = T18 | IOSTANDARD=LVCMOS18; # "BTNU"
Use the PlanAhead I/O pin planing (post synthesis) to see the results of the pin constraints
After downloading, you can see the LD0~LD7 flow effect on the board.
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