Original: In the process of arranging FPGA pins to generate ucf files, when there are more FPGA pins, manual routing of pins is not only inefficient, but also prone to errors. Pins can be easily and quickly implemented with tools such as PlanAhead and Adept. Especially when the pins to be arranged have a certain regularity or need to meet some conditions, the use of tools for pin arrangement has obvious advantages.
When a large number of pins need to be allocated, firstly, these pins need to be allocated to the specified area. For example, the pins of the same bus are allocated in the same bank, and all the pins of the same interface are allocated in several consecutive banks. Inside and so on. Therefore, you can first prepare an ucf, then enter the pins that need to be assigned, and only specify the net name and level standard. Then create a project for IO Planning in PlanAhead and import the ucf. If the imported pins are already arranged, you need to rearrange them. You can select all the pins to remove the existing ones. If there are differential signal lines, first bind the P and N of the differential signal lines. Then specify the disable pin in the selected bank and put the specified pin group (such as a bus) into this bank. The command used is place IO port in an IO bank. For different types of signals placed in the same bank, such as the normal data bus and clock input signals, all the clock function pins, VREF pins, and VRP/VRN functions of the bank can be disabled first, and then the data bus is disabled. Arrange and then turn off the clock function pin that is disabled, and then automatically arrange the clock function pins. In this way, all the pins are placed in the designated area in turn. At this point, all the pins have been arranged in each bank in a certain order, such as a bus with a bit width of 36 bits, and each pin in the bus is arranged in a continuous 36 tubes of the chip from small to large. Foot position; if it is a differential signal, the P/N pairs are placed on a pair of P/N pins of the bank. After completing this process, the pin layout results are exported to ucf, and then ucf is imported into Adept for small-scale adjustment. In the Adept interface, you can see the type of various pins in a bank. What you need to do now is to fine-tune the bank. Specifically, if the clock input does not follow the clock pin, you need to place the associated clock input on the SRCC or MRCC pin. If the bank has a pin level standard that requires VREF and DCI, you must The VREF and VRP/VRN pins are reserved and cannot be used as user pins. These operations can be done simply by performing a simple paste-copy command on the Adept interface, which is not easy to introduce a writing error and can be completed in a small amount of time. When these details are adjusted, the results can be exported to ucf again. At this time, the ucf pins are arranged neatly according to the bank, and are arranged in the same bank in order. On the basis of this ucf, a little finishing, the resulting ucf file is produced.
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