If you want to save its recording in digital form, you should convert its analog recording signal into digital form, which brings a lot of inconvenience to the preservation of the original data. Thus, according to the author G.723 standard design a digital recorder, it ADSP-2181 as a voice processor and a system controller, a mechanical part canceled and the tape recorder common to a large-capacity flash memory (Flash RAM ) As a digital voice data storage. The prototype is very small in size, has a long recording time, has no mechanical noise and mechanical failure, and is of practical value.
1 Introduction to G.723 standard and block diagram of system structure 1.1 Introduction to G.723 standard G.723 is a multimedia voice codec standard formulated by ITU-T in 1996. Typical applications include IP telephony services, H.324 video telephony, wireless telephony, digital satellite systems, digital power multiplication equipment (DCME), public switched telephone network (PSTN), ISDN, and various multimedia voice information products. G.723 standard transmission code rates are 5.3kb / s and 6.3kb / s, which can be switched at any time during the programming process. The standard mainly includes encoding algorithms and decoding algorithms. The principle is: parse out the channel model parameters from the collected voice signal, construct a synthesis filter, and use the appropriate excitation source to excite. The parameters of the coding transmission are mainly the parameters of the excitation source and the synthesis filter. The 5.3kb / s encoder uses algebraic line predictive excitation (ACELP); the 6.3kb / s encoder uses multi-pulse maximum likelihood quantization (MP-MLQ) excitation. According to the transmission coding parameters, the reconfigurable excitation source and the synthesis filter are decoded, and the recovered digital voice signal is converted into an analog voice signal by a D / A converter. For a detailed description of the encoding and decoding of G.723, see Reference [2].
The G.723 algorithm has a good encoding and decoding effect on voice signals, and can also process music and other sound signals. The typical input is 64kb / s (8k% 26; # 215; 8) or 128kb / s (8k% 26; # 215; 16) A-law or μ-law PCM sampling voice signal. Each time one frame of speech signal is processed, each frame has 240 sampling points (30ms). At a code rate of 5.3kb / s, each frame of speech is compressed into 20 bytes for transmission; at a code rate of 6.3kb / s, each frame of speech is compressed into 24 bytes for transmission.
1.2 Structural block diagram of digital recording system The system block diagram is mainly composed of the five parts shown in Figure 1.
AD73311 is used for A / D and D / A conversion, it integrates analog / digital and digital / analog conversion functions, and programmable control, extremely easy to use; ADSP-2181 is the core digital processor of the system [3], clock The frequency is 33MHz, and its function is strong; KM29N32000 is flash memory (Flash RAM), used to store compressed voice data; AT27C010 (EPROM) is used to store the program that controls the operation of ADSP-2181; LCD is used to display the current work of the system status. The work flow of the system is: the analog voice signal is sampled by AD73311 and compressed by A-law or μ-law, and then converted to PCM data, which is sent to ADSP-2181 through the serial port of ADSP-2181. ADSP-2181 then encodes and compresses the data Then send it to the flash memory KM29N32000 for storage; during recording playback, read the compressed data from KM29N32000, send it back to ADSP-2181 for decoding, and then send it to AD73311 for D / A conversion, output analog voice signal. The entire process is controlled by the DSP program stored in AT27C010 and works in an orderly manner. The LCD displays the current working status of the system.
2 The principle and interface of the main parts of the system 2.1 The interface circuit and programming control of AD73311 and ADSP-2181 2.1.1 The interface circuit of AD73311 and ADSP-2181 AD73311 has A / D and D / A conversion functions, the sampling frequency is 8kHz ～ 64kHz , Can be programmed and controlled, the sampling word length is 16 bits. AD73311 has a large signal-to-noise ratio, programmable input and output gain control, low operating voltage (2.7 ~ 5.5V), and a dual-purpose feature, it is a very popular chip. The interface circuit between AD73311 and ADSP-2181 is shown in Figure 2. AD73311 completes the collection of analog voice signals and the playback of digital voice signals. It can be seen from Figure 2 that the signal is input from VIN and the playback voice signal is output at VOUT. Connect a microphone at VIN and a speaker at VOUT. The communication with ADSP-2181 is carried out through the serial port, outputting data from SDO pin to ADSP-2181, and receiving ADSP-2181 data from SDI pin, sending and receiving can be performed simultaneously. The clock signal is accessed by the SLCK pin of ADSP-2181. When programming, you must first initialize the working state of the AD73311, set the sampling rate, input and output gain, and advance time in turn, and then let it work normally in the data transmission mode. AD73311 has been in A / D or D / A conversion after entering data transmission mode. In programming control, the serial port of ADSP-2181 should always work in the receiving interrupt mode, so that the data sending and receiving rate can be kept consistent. To change the operating mode, set its RESET pin low and then high, so that it can be reset.
2.1.2 Programming of AD73311
AD73311 is a programmable data converter, contains five 8-bit control registers CRA ~ CRE, used to set the working state, control input and output. The AD73311 communicates with the processor through a serial port and transmits 16-bit data. There are five working modes: program mode, data mode, mixed mode, analog loop mode, and digital loop mode. The first three are normal working modes, and the last two are debugging modes, which are only used during debugging. The five working modes are controlled by four bits (CRA0 ~ 3) in the internal control register A.
Program mode: The AD73311 works in program mode after startup or reset. At this time, the data input from the AD73311 serial port will be used as a command word to initialize the internal control register group. After that, the AD73311 enters the corresponding working mode according to the initialization command word. The code word output by the AD73311 serial port is invalid. Data mode: At this time, the AD73311 serial port outputs 16-bit data of A / D conversion, and the input is 16-bit data of D / A conversion. Once AD73311 enters data mode, it can no longer get control information, so it will always be in this mode unless restarted. At this time, the hardware can use the synchronization method of sending and receiving frame synchronization signals. Mixed mode: At this time, the 16-bit codeword may be a control word or data. The MSB of the code word is used to identify whether the code word is a control command word (MSB = 1) or data (MSB = 0, the lower 15 bits are valid data). In mixed mode, ADSP-2181 can change the working parameters of AD73311, such as the magnification of the amplifier, etc., according to the operating conditions of the system. At this time, the hardware can use the asynchronous method of sending and receiving frame synchronization signals to facilitate the autonomous control of ADSP-2181.
AD73311 controls the sampling rate by the clock frequency dividing circuit. The clock frequency dividing circuit divides the external clock frequency MCLK input from the DMCLK pin into the internal clock frequency DMCLK by the main frequency clock factor. MCLK has five frequency options, which are controlled by three bits CRB4 ~ 6 in the internal control register B. DMCLK determines the sampling frequency of AD73311, which is also the frame synchronization frequency of the serial port of AD73311. DMCLK is divided into serial clock frequency SCLK by serial clock dividing factor again, DMCLK has four kinds of choices, controlled by GRG2 ~ 3 two bits in the internal control register B.
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